Electronic System Design Group
Changelog¶
0.4.2 2019.07.17
- [Bug]: Workaround to prevent Sphinx from processing non-html files when parsing documentation generated using Doxygen.
- [Support]: Added argument to allow skipping of XML2VHDL generation.
--skip_xml2vhdl
0.4.0 2019.03.20
- [Support] #4:: Added
git
support for cloning dependencies fromgit
repositories. Renamed$REPO_USERNAME
$SVN_USERNAME
to allow the script to differentiate betweengit
andsvn
repositories. This requires an update to~/.cshrc
beforeFPGAFlow
will execute successfully.
0.3.7 2019.03.17
- [Bug]: Fixed path locations for documentation templates when executing
FPGAFlow
from a virtual environment. - [Bug]: Fixed running project without specifying a board.
- [Bug] #3: Fixed issue where
--clean precompiled_sim
failed to clean the pre-compiled simulation libraries and--clean fpga
failed to clean (and backup) the project build location. - [Support]: Overrides the
vunit_args: num_threads:
value in the corresponding settings YAML file if--open_project sim
is used. This is to prevent multiple Modelsim GUI instances from spawning when using this command line argument. - [Support]: Tag replacement runs when setting
$LD_LIBRARY_PATH
from configuration YAML file. - [Support] #1: Add Bamboo support to
FPGAFlow
. - [Support] #2: Fixed issue where
build
in$REPO_ROOT
or${bamboo.REPO_ROOT}
prevents any source code from being added byFPGAFlow
.
0.3.6 2019.03.06
- [Bug]: Fixed file paths to referenced files in packaged version.
- [Support]: Moved
xml2vhdl
usage fromsys.path
addition to using packaged version. This is now included in thePipfile
, assumingxml2vhdl
is checked out under$REPO_ROOT/tools/xml2vhdl
- [Support]: Added support for searching for and adding HDL test-benches to corresponding libraries within
the
VUnit
object. - [Support]:
projectflow.ProjectFlow
Checks if test-bench simulation files exist matching theself.top_level_tb_entity[0]
value from Settings. - [Support]:
fpgavendor_iface.FpgaProject.create_quartus_project
adds top-level HDL test-bench toquartus
project if it is successfully located on the file-system. - [Support]: Added
funcs.vunit_tb_cfg_encode
to handle global encoding ofVUnit
test-bench configuration when runningVUnit
. - [Support]: Updated
arguments
andvuint_iface.VUnitProject
to handle additional arguments required byvunit_hdl>=0.3.9
which preventedVUnit
from running test-cases. - [Support]: Passing
--open_gui sim
and--clean all
--clean sim
arguments toVUnit
.
0.3.5 2019.03.05
- [Feature]: Added generation of timestamp parameter for automatically inserting a Unix timestamp into the
HDL top-level via a generic entry. This can be enabled/disabled from the board settings file using the:
board_timestamp_enabled: <True|False>
option. - [Feature]: Added generation of
board_id
parameter for automatically inserting aboard_id
into the HDL top-level via a generic entry. This can be configured from the board settings file using the:board_id: "00000000"
option. Where the ID is a hex presentation of a 32 bit unsigned number. - [Feature]:
fpgavendor_iface.FpgaProject.create_quartus_project
now replaces all absolute paths with$env(REPO_ROOT)
, this means that the resultingproject_gen.tcl
has no references to the users working location and can be committed in the revision control system. When copying.qsf
files line-by-line, blanks and commented-out lines are ignored, if the user wants comments to be copied the script will add any comment starting with more than one#
comment character. - [Feature]: Added Argument parsing for
--open_gui
and--clean
, see Arguments. These arguments depreciate options in the Settings. Converted--checkout_disabled
to--checkout_enabled
as the majority of user use cases are working on checked out locations. - [Bug]:
qsys-generate
now generates both for synthesis and simulation. When parsing the generated Modelsim generation script, the top-level simulation file is now added to the VUnit object to a HDL library matching the top-level HDL file for the IP. This matches the configuration as described in the corresponding generated.qip
file. - [Bug]: Fixed issue hen parsing enabled
vendor_ip
in project where common wrapper file location was being to aggressive on determining wrapper file search path. Search locations are determined by: 1. wrapper file directory matches the IP name and 2. wrapper file directory matches the IP wrapper name (with_wrapper
suffix stripped). - [Bug]: Fixed issue where
docflow.ProjectDoc.generate_automodule
added duplicate entries for modules found in the /build and /dist paths. - [Support]: Fixed duplication of project name when building projects if board name and project name match.
- [Support]: Modified build path creation. If the build path is in
boards
the script will no longer duplicatevendor
andtool_version
in the constructed build path, as they already exist for theboard
being targeted. - [Support]: Added
MANIFEST.in
to include all files required byFPGAflow
toPyPi
. - [Support]: Restructured layout of
FPGAFlow
to allow for use ofsetuptools
. Addedsetup
which can be executed using:python setup.py sdist bdist_wheel
from:$REPO_ROOT/tools/fpgaflow/scripts/python/fpgaflow-esdg
0.3.3 2019.02.25
- [Bug]: Fixed type in
vunit_iface
which caused default language to always be used when compiling standard libraries for Modelsim by invokingquartus
. - [Bug]: Fixed issue with
--checkout_disabled
and--dev
argument usage evaluating against the str"False"
rather than the booleanFalse
which prevented SVN checkouts. - [Bug]: Fixed issue where duplicate
vendor_ip
wrapper files were added toVUnit
. - [Bug]: Fixed issue where missing
vendor_ip
locations caused the script to crash. Now they raise a critical warning. - [Bug]: Fixed issue where double slashes:
//
in$REPO_ROOT
causesVUnit
to fail to get sourcefile objects. - [Support]: Added
fpgavendor_iface
module - [Support]: Added provision to compile standard libraries for Modelsim by invoking
vivado
. - [Support]: Added
glbl
support forvivado
based simulations. - [Support]: Added provision to compile standard libraries for Modelsim by invoking
quartus
. Convertedfpgavendor_iface.run_quartus_sh
andfpgavendor_iface.run_vivado
from positional arguments to keyword arguments. - [Support]: Added
projectflow.ProjectFlow.generate_project_name
. - [Support]: Added support for
boards
. Boards are now handled in the same way as project dependencies. - [Support]: Added support for mapping top-level directory names to other values.
projectmanager.ProjectDependency.top_dir_lookup
. Added documentation: Directory Layouts - [Support]: Added
vendor_ip_handler
to processvendor_ip
design files. - [Support]: Added
board_handler
to processboard
design files, which overwrites project settings to target specific hardware. - [Support]: Updated
vendor_ip
support. Changed method to add IP files and Wrapper Files. - [Support]: Removed
vendor_ip_handler
. This is now handled byprojectflow
andprojectmanager
- [Support]: Removed
board_handler
. This is now handled byprojectflow
andprojectmanager
- [Support]: Added
fpgavendor_iface.FpgaProject.create_quartus_project
which creates a line-by-linetcl
script to generate aquartus
project file. HDL source files are determined fromVUnit
object which has all foundhdl
files in the project. If a top-level board file fails to include the project’s top-level file the script will add the top-level project file and dependencies, but until a a project to board mechanism is developed the project to board wrapper will need to be manually added. - [Support]: Added constraint file processing to
projectflow.ProjectFlow
. - [Support]: Generated
project_gen.tcl
is now generated in the root project build path. Generates quartus project, and usesrebuild_project: <True|False>
settings value to determine if existing projects should be backed up. - [Support]: Added Known Issues to document problems and solutions to problems executing the script.
- [Support]: Added
fpgavendor_iface.run_ip_setup_simulation
to processquartus
project file for extractingvendor_ip
simulations files. - [Support]: Added
fpgavendor_iface.run_ip_generate
to generatequartus
vendor_ip. - [Support]: Added
vunit_iface.compile_project_ip
to compile vendor_ip simulation files from enabled vendor_ip. - [Support]: Added
--open_project
argument, which opens generated project in GUI. - [Support]: Parses vendor_ip simulation compile order, derived from quartus project, and adds libraries and HDL to VUnit object.
0.3.2 2019.01.31
- [Bug]: Fixed issue where relative paths in
docflow
were incorrectly relative to the calling location when generating documentation for other modules. - [Bug]: Fixed bug where vendor specific HDL source code was not filtered when adding to
VUnit
. - [Support]: Added
documentation: header:
support for modifying the common header used in generatedsphinx
documentation - [Support]: Expanded automodule exclude term to include
template
instead oftemplates
. - [Support]: Added
XML2VHDL
dependency checking inprojectflow
to ensure that required VHDL libraries are included before proceeding. - [Support]: Added
required_vhdl_libs
option forXML2VHDL
VHDL library checking in settings file. - [Support]: Added
projectflow.Xml2Vhdl
to create object for executingxml2vhdl
script. - [Support]: Added complete set of attributes to replicate arguments to pass to
xml2vhdl
script. - [Support]: Moves into
xml2vhdl
script directory to executexml2vhdl
, returns toprojectflow
working directory when complete. - [Support]: Added support for adding other FPGA vendors to
exclude_terms
based on Configuration file. See supported_vendors:. - [Support]: Added support for getting
exclude_terms
from Configuration file. See exclude_keywords:. - [Support]: Added
projectflow.ProjectFlow.search_paths_for_files
to recursively search paths taking into accountexclude_terms
and EXCLUDE Files - [Support]: Added
vunit-hdl
for managing and processing HDL designs and simulations. - [Support]: Added
projectflow.ProjectFlow.get_top_level_files
to find top-level HDL files in list of HDL files. If none are defined in top_level: the script will exit. - [Support]: Added
arguments.Arguments._vunit_args
which addsVUnit
Argument passing from Settings instead of command line. Addedargs
as attribute toenvironmentsetup.ProjectEnvironment
for use inprojectflow
. - [Support]: Moved
projectflow.Xml2Vhdl
toxml2vhdl_iface
to tidy up source code. - [Support]: Moved
projectflow.VUnitProject
tovunit_iface
to tidy up source code. - [Support]: Added documentation for vunit_args: to Settings.
- [Support]: Added
no_color
argument support forVUnit
- [Support]: Added
sim_init_script
VUnit
support for running GUI mode. Added--headless
argument processing to override GUI options.
0.3.1 2019.01.23
- [Support]: Fixed Release number in Documentation
0.3.0 2019.01.23
- [Support]: Now using
action="store_true"
forarguments
which will set optional arguments toTrue
if present,False
otherwise. - [Support]: Added support for
bitbucket
username retrieved from system environment variable. - [Support]: Uses
urlparse
to process URL construction for remote repository paths. - [Support]:
projectmanager
now processes bothgit
andsubversion
repository locations. - [Support]: Renamed
helper
helpers
to prevent namespace conflicts when importingxml2vhdl
. This is a temporary workaround. - [Support]: Added
numpy
to python virtual environment.
0.2.0 2019.01.15
- [Support]: Removed obsolete
errorhandling.py
helper module. - [Support]: Added docstrings for helper modules.
- [Support]: Grouped helper modules to tidy up documentation.
- [Support]: Updated docstring documentation for
projectmanager
- [Support]: Added description of
repository_config:
to the Settings document. - [Support]: Updated docstring documentation for
environmentsetup
- [Support]: Added simulation: description to Configuration documentation page.
- [Support]: Added in depth descriptions for Settings documentation page.
- [Support]: Added fpga: descriptions in Configuration documentation.
- [Support]: Added LICENCE to each python module.
- [Support]: Alphabetical ordering of index and modules, based on filename not title.
0.1.0 2019.01.14
- [Feature]: Added
releases
support with this changelog file. - [Support]: Updating documentation for
docflow
- [Support]: Fixed external links in documentation, fixed readthedocs badge usage.
- [Support]: Added License link in README.
- [Support]: Completed docstring documentation for
sphinx
based functions indocflow
- [Support]: Completed docstring documentation for
doxygen
based functions indocflow
- [Support]: Started to update docstring documentation for
version
andarguments