helpers/arguments.py
helpers/customlogging.py
docflow.py
environmentsetup.py
fpgavendor_iface.py
helpers/funcs.py
projectmanager.py
setup.py
helpers/version.py
vunit_iface.py
--config
--settings
--checkout_enabled
--headless
--skip_xml2vhdl
--open_gui
fpga
sim
--clean
all
ip
precompiled_sim
repository:
required:
categories:
category_mapping:
lib_append_categories:
<CATEGORY>_layout:
contributors:
contrib_lib_list:
fpga:
supported_vendors:
<FPGA VENDOR>:
simulation:
<SIM TOOL VENDOR>:
xilinx:
altera:
vhdl:
documentation:
supported_languages:
doxygen:
sphinx:
dot:
environment:
exclude_keywords:
constraints
docs
netlists
scripts
settings
simulation
src
<CATEGORY>:
name:
contrib_lib:
top_level:
top_level_tb_entity:
vendor:
family:
tool_version:
tool_mode:
device:
board_id:
board_timestamp_enabled:
board:
board_settings:
project_name_override:
sim_vendor:
sim_version:
sim_mode:
sim_init_script:
use_glbl:
vunit_args:
version:
list:
files:
log_level:
output_path:
test_patterns:
keep_compiling:
num_threads:
elaborate:
verbose:
xunit_xml:
coverage:
unique_sim:
exit_0:
no_color:
xunit_xml_format:
dont_catch_exceptions:
export_json:
with_attributes:
without_attributes:
compile:
fail_fast:
repository_config:
git:
subversion:
project_title:
project_version:
project_author:
project_org:
project_release:
doxy_version:
dot_version:
sphinx_version:
image_path:
logo_path:
logo_name:
source_path:
language:
restricted_src:
doc_clean:
release_uri:
issue_uri:
releases_document_name:
doxy_mainpage:
pipenv_installer.py
vendor_ip_layout: